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XC95144XV High-Performance CPLD
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DS051 (v2.2) August 27, 2001
Advance Product Specification
Features
* * 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81 user I/O pins) - 144-pin TQFP (117 user I/O pins) - 144-pin CSP (117 user I/O pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Two separate output banks - Superior pin-locking and routability with FastCONNECT IITM switch matrix - Extra wide 54-input Function Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard 1149.1 boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of ICC, the following equation may be used: ICC (mA) = MCHP(0.36) + MCLP(0.23) + MC(0.005 mA/MHz) f Where: MCHP = Macrocells in high-performance (default) mode MCLP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Function Block with no output loading. The actual ICC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form.
200 200 MHz
*
*
* * * *
150 Typical ICC (mA) 120 MHz 100
H ig hP erfo rm e anc
Description
The XC95144XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight 54V18 Function Blocks, providing 3,200 usable gates with propagation delays of 4 ns.
Low
P ow
er
50
0
40
120 80 Clock Frequency (MHz)
160
200
DS051_01_012501
Figure 1: Typical ICC vs. Frequency for XC95144XV
(c) 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
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3 JTAG Port 1
JTAG Controller
In-System Programming Controller
54 I/O I/O I/O FastCONNECT II Switch Matrix I/O 54 18 18
Function Block 1 Macrocells 1 to 18
Function Block 2 Macrocells 1 to 18
I/O Blocks I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS 4
54 18
Function Block 3 Macrocells 1 to 18
54 18
Function Block 4 Macrocells 1 to 18
54 18
Function Block 8 Macrocells 1 to 18
DS051_02_041000
Figure 2: XC95144XV Architecture Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
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DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
Absolute Maximum Ratings
Symbol VCC VCCIO VIN VTS TSTG TSOL TJ Description Supply voltage relative to GND Supply voltage for output drivers Input voltage relative to GND(1) Value -0.5 to 2.7 -0.5 to 3.6 -0.5 to 3.6 -0.5 to 3.6 -65 to +150 +260 +150 Units V V V V
oC oC oC
Voltage applied to 3-state output(1) Storage temperature (ambient) Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm) Junction temperature
Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Recommended Operation Conditions
Symbol VCCINT Parameter Supply voltage for internal logic and input buffers Commercial TA = 0oC to +70oC Industrial TA = -40oC to +85oC Min 2.37 2.37 3.13 2.37 1.71 0 1.7 0 Max 2.62 2.62 3.46 2.62 1.89 0.8 3.6 VCCIO V V V V V V Units V
VCCIO
Supply voltage for output drivers for 3.3V operation Supply voltage for output drivers for 2.5V operation Supply voltage for output drivers for 1.8V operation
VIL VIH VO
Low-level input voltage High-level input voltage Output voltage
Quality and Reliability Characteristics
Symbol TDR NPE VESD Data retention Program/Erase cycles (endurance) Electrostatic Discharge (ESD) Parameter Min 20 10,000 2,000 Max Units Years Cycles Volts
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XC95144XV High-Performance CPLD
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DC Characteristics (Over Recommended Operating Conditions)
Symbol VOH Parameter Output high voltage for 3.3V outputs Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs VOL Output low voltage for 3.3V outputs Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs IIL Input leakage low current Test Conditions IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 1.0 mA IOL = 100 A VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VCC = 2.62V VCCIO = 3.6V VIN = GND or 3.6V VIN = GND f = 1.0 MHz VI = GND, No load f = 1.0 MHz Min 2.4 2.0 90% VCCIO Max 0.4 0.4 0.4 10 Units V V V V V V A
IIH
Input leakage high current
-
10
A
CIN ICC
I/O capacitance Operating Supply Current (low power mode, active)
29
10
pF mA
AC Characteristics
XC95144XV-4 Symbol TPD TSU TH TCO fSYSTEM TPSU TPH TPCO TOE TOD TPOE TPOD TAO TPAO TWLH TPLH Parameter I/O to output valid I/O setup time before GCK I/O hold time after GCK GCK to output valid Multiple FB internal operating frequency I/O setup time before p-term clock input I/O hold time after p-term clock input P-term clock output valid GTS to output valid GTS to output disable Product term OE to output enabled Product term OE to output disabled GSR to output valid P-term S/R to output valid GCK pulse width (High or Low) P-term clock pulse width (High or Low) Min 2.8 0 0.8 2.0 2.0 5.0 Max 4.0 2.8 250.0 4.8 3.2 3.2 5.6 5.6 7.9 8.5 XC95144XV-5 Min 3.5 0 1.0 2.5 2.2 5.0 Max 5.0 3.5 222.2 6.0 4.0 4.0 7.0 7.0 10.0 10.7 XC95144XV-7 Min 4.8 0 1.6 3.2 4.0 6.5 Max 7.5 4.5 125.0 7.7 5.0 5.0 9.5 9.5 12.0 12.6 Units ns ns ns ns MHz ns ns ns ns ns ns ns ns ns ns ns
Advance Information
Notes: 1. Please contact Xilinx for up-to-date information on advance specifications. 4 www.xilinx.com 1-800-255-7778
Preliminary Information
DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
VTEST R1 Device Output R2 CL
Output Type
VCCIO 3.3V 2.5V 1.8V
VTEST 3.3V 2.5V 1.8V
R1 320 250 10K
R2 360 660 14K
CL 35 pF 35 pF 35 pF
DS051_03_0601000
Figure 3: AC Load Circuit
Internal Timing Parameters
XC95144XV-4 Symbol Buffer Delays TIN TGCK TGSR TGTS TOUT TEN TPTCK TPTSR TPTTS TPDI TSUI THI TECSU TECHO TCOI TAOI TRAI TLOGI TLOGILP TF TPTA TPTA2 TSLEW Input buffer delay GCK buffer delay GSR buffer delay GTS buffer delay Output buffer delay Output buffer enable/disable delay Product term clock delay Product term set/reset delay Product term 3-state delay Combinatorial logic propagation delay Register setup time Register hold time Register clock enable setup time Register clock enable hold time Register clock to output valid time Register async. S/R to output delay Register async. S/R recover before clock Internal logic delay Internal low power logic delay FastCONNECT IITM feedback delay Incremental product term allocator delay Adjacent macrocell p-term allocator delay Slew-rate limited delay 1.6 1.2 1.6 1.2 4.0 0.6 5.6 1.6 0.6 0.2 1.6 1.0 1.6 3.2 1.6 0 1.4 0.6 4.0 0.2 0.2 4.7 2.0 1.5 2.0 1.5 5.0 0.7 5.7 1.6 0.7 0.3 2.0 1.2 2.0 4.0 2.1 0 1.7 0.7 5.0 0.2 0.2 5.9 2.6 2.2 2.6 2.2 7.5 1.4 6.4 3.5 0.8 0.3 2.3 1.5 3.1 5.0 2.5 0 2.4 1.4 7.2 1.3 0.5 6.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min Max XC95144XV-5 Min Max XC95144XV-7 Min Max Units
Product Term Control Delays
Internal Register and Combinatorial Delays
Feedback Delays Time Adders
3.0 Advance Information
3.0 4.0 Preliminary Information
Notes: 1. Please contact Xilinx for up-to-date information on advance specifications.
DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
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XC95144XV I/O Pins
Function MacroTQ100 Block cell TQ144 CS144 BScan Order
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -
Function MacroBlock cell
TQ100
TQ144
CS144
BScan Order
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
11 12 13 14 15 16 17 18 19 20 22(1) 99(1) 1(1) 2(1) 3(1) 4(1) 6 7 8 9 10 -
23 16 17 25 19 20 21 22 31 24 26 27 28 35 30(1) 142 143(1) 4 2(1) 3(1) 5(1) 6(1) 7 9 10 12 11 13 14 15 -
H3 F1 G2 J1 G3 G4 H1 H2 K3 H4 J2 J3 J4 M1 K2(1) C3 A2(1) C1 B1(1) C2(1) D4(1) D3(1) D2 E4 E3 E1 E2 F4 F3 F2 -
429 426 423 420 417 414 411 408 405 402 399 396 393 390 387 384 381 378 375 372 369 366 363 360 357 354 351 348 345 342 339 336 333 330 327 324
3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
23(1) 24 25 27(1) 28 29 30 32 33 34 87 89 90 91 92 93 94 95 96 97 -
39 32(1) 41 44 33 34 46 38(1) 40 48 43 45 49 50 51 118 126 133 128 129 130 131 135 132 134 137 136 138 139 140 -
M3 L1(1) K4 N4 L2 L3 L5 N2(1) N3 N5 M4 K5 K6 L6 M6 C9 A7 A5 D7 A6 B6 C6 C5 D6 B5 A4 D5 B4 C4 A3 -
321 318 315 312 309 306 303 300 297 294 291 288 285 282 279 276 273 270 267 264 261 258 255 252 249 246 243 240 237 234 231 228 225 222 219 216
Notes: 1. Global control pin.
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DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
Function MacroBlock cell
TQ100
TQ144
CS144
BScan Order Bank
Function Block
Macrocell
TQ100
TQ144
CS144
BScan Order
Bank 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -
5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
35 36 37 39 40 41 42 43 46 49 74 76 77 78 79 80 81 82 85 86 -
52 59 53 54 66 56 57 68 58 60 70 61 64 69 106 111 110 112 113 116 115 119 120 121 124 117 125 -
N6 L8 M7 N7 M10 K7 N8 N11 M8 K8 L11 N9 K9 M11 C11 B11 A12 A11 D10 A10 B10 B9 A9 D8 A8 D9 B7 -
213 210 207 204 201 198 195 192 189 186 183 180 177 174 171 168 165 162 159 156 153 150 147 144 141 138 135 132 129 126 123 120 117 114 111 108
1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 -
7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
50 52 53 54 55 56 58 59 60 61 63 64 65 66 67 68 70 71 72 73 -
71 75 74 76 77 78 80 79 82 85 81 86 87 83 88 91 95 97 92 93 94 96 101 98 100 103 102 104 107 105 -
N12 L12 M13 L13 K10 K11 K13 K12 J11 H10 J10 H11 H12 J12 H13 G11 F11 E13 G10 F13 F12 F10 D13 E12 E10 D11 D12 C13 B13 C12 -
105 102 99 96 93 90 87 84 81 78 75 72 69 66 63 60 57 54 51 48 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0
DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
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XC95144XV Global, JTAG and Power Pins
Pin Type I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GTS3 I/O/GTS4 I/O/GSR TCK TDI TDO TMS VCCINT 2.5V VCCIO1 VCCIO2 GND TQ100 22 23 27 3 4 1 2 99 48 45 83 47 5, 57, 98 26, 38, 51 88 21, 31, 44, 62, 69, 75, 84, 100 TQ144 30 32 38 5 6 2 3 143 67 63 122 65 8, 42, 84, 141 37, 55, 73 1, 109, 127 18, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, 144 CS144 K2 L1 N2 D4 D3 B1 C2 A2 L10 L9 C8 N10 B3, D1, J13, L4 L7, N1, N13 A1, A13, C7 B2, B8, B12, C10, E11, G1, G12, G13, K1, M2, M5, M9, M12 -
No Connects
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DS051 (v2.2) August 27, 2001 Advance Product Specification
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XC95144XV High-Performance CPLD
Ordering Information
Example:
Device Type Speed Grade
XC95144XV -7 TQ 100 C
Temperature Range Number of Pins Package Type
Device Ordering Options
Speed -7 -5 -4 7.5 ns pin-to-pin delay 5 ns pin-to-pin delay 4 ns pin-to-pin delay TQ100 TQ144 CS144 Package 100-pin Thin Quad Flat Pack (TQFP) 144-pin Thin Quad Flat Pack (TQFP) 144-ball Chip Scale Package (CSP) I = Industrial Temperature C = Commercial TA = 0C to +70C TA = -40C to +85C
Component Availability
Pins Type Code XC95144XV -7 -5 -4 100 Plastic TQFP TQ100 C, I (C) (C) 144 Plastic TQFP TQ144 C, I (C) (C) 144 Plastic CSP CS144 C (C) -
Notes: 1. C = Commercial (TA = 0oC to +70oC); I = Industrial (TA = -40oC to +85oC). 2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information.
Revision History
The following table shows the revision history for this document.. Date 06/28/00 01/25/01 05/15/01 08/27/01 Version 1.0 2.0 2.1 2.2 Revision Initial Xilinx release. Advance information specification. Added -4 performance specifications.Updated ICC vs. Frequency Figure 1. Updated ICC formula, Recommended Operation Conditions, -4 and -5 AC Characteristics and Internal Timing Parameters Changed VCCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: IIL added "low" current, IIH - changed to "Input leakage high current"; Internal Timing: -5 TAOI from 6.5 to 5.9.
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